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KELEFOURAS, Vasileios, KRITIKAKOU, Angeliki and GOUTIS, Costas (2014). A Matrix--Matrix Multiplication methodology for single/multi-core architectures using SIMD. The Journal of Supercomputing, 68 (3), 1418-1440.
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Kelefouras-Matrix-MatrixMultiplicationMethodologyforSIngleMulti-Core(AM).pdf - Accepted Version All rights reserved. Download (1MB) | Preview |
Abstract
In this paper, a new methodology for speeding up Matrix–Matrix Multiplication using Single Instruction Multiple Data unit, at one and more cores having a shared cache, is presented. This methodology achieves higher execution speed than ATLAS state of the art library (speedup from 1.08 up to 3.5), by decreasing the number of instructions (load/store and arithmetic) and the data cache accesses and misses in thememory hierarchy. This is achieved by fully exploiting the software characteristics (e.g. data reuse) and hardware parameters (e.g. data caches sizes and associativities) as one problem and not separately, giving high quality solutions and a smaller search space.
| Item Type: | Article |
|---|---|
| Departments - Does NOT include content added after October 2018: | Faculty of Science, Technology and Arts > Department of Computing |
| Identification Number: | https://doi.org/10.1007/s11227-014-1098-9 |
| Page Range: | 1418-1440 |
| Depositing User: | Vasileios Kelefouras |
| Date Deposited: | 27 Mar 2018 11:26 |
| Last Modified: | 18 Mar 2021 15:19 |
| URI: | https://shura.shu.ac.uk/id/eprint/18355 |
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