Cache partitioning + loop tiling: A methodology for effective shared cache management

KELEFOURAS, Vasileios, KERAMIDAS, Georgios and VOROS, Nikolaos (2017). Cache partitioning + loop tiling: A methodology for effective shared cache management. In: HÜBNER, Michael, REIS, Ricardo, STAN, Mircea and VOROS, Nikolaos, (eds.) 2017 IEEE Computer Society Annual Symposium on VLSI (ISVLSI) : Emerging VLSI technologies and architectures. Bochum, Germany, IEEE Computer Society, 477-482.

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Official URL: https://ieeexplore.ieee.org/document/7987565/
Link to published version:: https://doi.org/10.1109/ISVLSI.2017.89
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    Abstract

    In this paper, we present a new methodology that provides i) a theoretical analysis of the two most commonly used approaches for effective shared cache management (i.e., cache partitioning and loop tiling) and ii) a unified framework to fine tuning those two mechanisms in tandem (not separately). Our approach manages to lower the number of main memory accesses by one order of magnitude keeping at the same time the number of arithmetical/addressing instructions in a minimal level. We also present a search space exploration analysis where our proposal is able to offer a vast deduction in the required search space.

    Item Type: Book Section
    Additional Information: Paper presented at the 2017 IEEE Computer Society Annual Symposium on VLSI (ISVLSI). Bochum Germany, 3-5 July 2017. INSPEC Accession Number: 17059635 Electronic ISSN: 2159-3477
    Departments - Does NOT include content added after October 2018: Faculty of Science, Technology and Arts > Department of Computing
    Identification Number: https://doi.org/10.1109/ISVLSI.2017.89
    Page Range: 477-482
    Depositing User: Vasileios Kelefouras
    Date Deposited: 09 May 2018 14:49
    Last Modified: 16 May 2018 16:49
    URI: http://shura.shu.ac.uk/id/eprint/18358

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