Area-throughput trade-offs for SHA-1 and SHA-256 hash functions’ pipelined designs

MICHAIL, Harris E., ATHANASIOU, George S., KELEFOURAS, Vasileios, THEODORIDIS, George, STOURAITIS, Thanos and GOUTIS, Costas E. (2016). Area-throughput trade-offs for SHA-1 and SHA-256 hash functions’ pipelined designs. Journal of Circuits, Systems and Computers, 25 (04), p. 1650032.

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Official URL: http://www.worldscientific.com/doi/abs/10.1142/S02...
Link to published version:: 10.1142/S0218126616500328

Abstract

High-throughput designs of hash functions are strongly demanded due to the need for security in every transmitted packet of worldwide e-transactions. Thus, optimized and non-optimized pipelined architectures have been proposed raising, however, important questions. Which is the optimum number of the pipeline stages? Is it worth to develop optimized designs or could the same results be achieved by increasing only the pipeline stages of the non-optimized designs? The paper answers the above questions studying extensively many pipelined architectures of SHA-1 and SHA-256 hashes, implemented in FPGAs, in terms of throughput/area (T/A) factor. Also, guides for developing efficient security schemes designs are provided. Read More: https://www.worldscientific.com/doi/abs/10.1142/S0218126616500328

Item Type: Article
Uncontrolled Keywords: Hash function; message authentication code; pipeline; FPGA, security
Departments: Arts, Computing, Engineering and Sciences > Computing
Identification Number: 10.1142/S0218126616500328
Depositing User: Vasileios Kelefouras
Date Deposited: 27 Mar 2018 09:33
Last Modified: 27 Mar 2018 09:40
URI: http://shura.shu.ac.uk/id/eprint/18342

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