On the Exploitation of a High-throughput SHA-256 FPGA Design for HMAC

MICHAIL, Harris E., ATHANASIOU, George S., KELEFOURAS, Vasileios, THEODORIDIS, George and GOUTIS, Costas E. (2012). On the Exploitation of a High-throughput SHA-256 FPGA Design for HMAC. ACM Transactions on Reconfigurable Technology and Systems (TRETS), 5 (1), 2:1-2:28.

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Official URL: http://doi.acm.org/10.1145/2133352.2133354
Link to published version:: https://doi.org/10.1145/2133352.2133354


High-throughput and area-efficient designs of hash functions and corresponding mechanisms for Message Authentication Codes (MACs) are in high demand due to new security protocols that have arisen and call for security services in every transmitted data packet. For instance, IPv6 incorporates the IPSec protocol for secure data transmission. However, the IPSec's performance bottleneck is the HMAC mechanism which is responsible for authenticating the transmitted data. HMAC's performance bottleneck in its turn is the underlying hash function. In this article a high-throughput and small-size SHA-256 hash function FPGA design and the corresponding HMAC FPGA design is presented. Advanced optimization techniques have been deployed leading to a SHA-256 hashing core which performs more than 30% better, compared to the next better design. This improvement is achieved both in terms of throughput as well as in terms of throughput/area cost factor. It is the first reported SHA-256 hashing core that exceeds 11Gbps (after place and route in Xilinx Virtex 6 board).

Item Type: Article
Uncontrolled Keywords: Hash functions, fpga, message authentication codes, security
Departments - Does NOT include content added after October 2018: Faculty of Science, Technology and Arts > Department of Computing
Identification Number: https://doi.org/10.1145/2133352.2133354
Page Range: 2:1-2:28
Depositing User: Vasileios Kelefouras
Date Deposited: 05 Apr 2018 13:46
Last Modified: 18 Mar 2021 15:19
URI: https://shura.shu.ac.uk/id/eprint/18348

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