STEWART, Robert, MICHAELSON, Greg, BHOWMIK, Deepayan, GARCIA, Paulo and WALLACE, Andy (2016). A dataflow IR for memory efficient RIPL compilation to FPGAs. In: CARRETERO, Jesus, GARCIA-BLAS, Javier, GERGEL, Victor, VOEVODIN, Vladimir, MEYEROV, Iosif, RICO-GALLEGO, Juan A., DIAZ-MARTIN, Juan C., ALONSO, Pedro, DURILLO, Juan, GARCIA SANCHEZ, Jose Daniel, LASTOVETSKY, Alexey L., MAROZZO, Fabrizio, LIU, Qin, BHUIYAN, Zakirul Alam, FURLINGER, Karl, WEIDENDORFER, Josef and GARCIA, Jose, (eds.) Algorithms and architectures for parallel processing : ICA3PP 2016 Collocated Workshops: SCDT, TAPEMS, BigTrust, UCER, DLMCS, Granada, Spain, December 14-16, 2016, Proceedings. Lecture Notes in Computer Science (10049). Springer, 174-188. [Book Section]
Bhowmik - Dataflow IR for memory efficient RIPL (AM).pdf - Accepted Version
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