A nonuniform DPLL architecture for optimized performance

This paper presents the design, analysis, simulation and implementation of the architecture of a new non-uniform type digital phaselocked loop (DPLL). The proposed loop uses a composite phase detector (CPD), which consists of a sample-and-hold unit and an arctan block. The CPD improves the system linearity and results in a wider lock range. In addition, the loop has an adaptive controller block, which can be used to minimize the overall system sensitivity to variations in the power of the input signal. Furthermore, the controller has a tuning mechanism that gives the designer the flexibility to customize the loop parameters to suit a particular application. These performance parameters include lock range, acquisition time, phase noise or jitter, and signal to noise ratio enhancement. The simulation results show that the proposed loop provides flexibility to optimize the major conflicting system parameters. A prototype of the proposed system was implemented using an FPGA and the practical results concur with those obtained by simulation using MATLAB/Simulink.