Optimized memory allocation and power minimization for FPGA-based image processing

GARCIA, Paulo, BHOWMIK, Deepayan, STEWART, Robert, MICHAELSON, Greg and WALLACE, Andrew (2019). Optimized memory allocation and power minimization for FPGA-based image processing. Journal of Imaging, 5 (1), p. 7.

[img]
Preview
PDF
Bhowmik-OptimizedMemoryAllocation(VoR).pdf - Published Version
Creative Commons Attribution.

Download (2MB) | Preview
Official URL: https://www.mdpi.com/2313-433X/5/1/7
Open Access URL: https://www.mdpi.com/2313-433X/5/1/7 (Published version)
Link to published version:: https://doi.org/10.3390/jimaging5010007

Abstract

Memory is the biggest limiting factor to the widespread use of FPGAs for high-level image processing, which require complete frame(s) to be stored in situ. Since FPGAs have limited on-chip memory capabilities, efficient use of such resources is essential to meet performance, size and power constraints. In this paper, we investigate allocation of on-chip memory resources in order to minimize resource usage and power consumption, contributing to the realization of power-efficient high-level image processing fully contained on FPGAs. We propose methods for generating memory architectures, from both Hardware Description Languages and High Level Synthesis designs, which minimize memory usage and power consumption. Based on a formalization of on-chip memory configuration options and a power model, we demonstrate how our partitioning algorithms can outperform traditional strategies. Compared to commercial FPGA synthesis and High Level Synthesis tools, our results show that the proposed algorithms can result in up to 60% higher utilization efficiency, increasing the sizes and/or number of frames that can be accommodated, and reduce frame buffers’ dynamic power consumption by up to approximately 70%. In our experiments using Optical Flow and MeanShift Tracking, representative high-level algorithms, data show that partitioning algorithms can reduce total power by up to 25% and 30%, respectively, without impacting performance.

Item Type: Article
Uncontrolled Keywords: field programmable gate array (FPGA); memory; power; image processing; design
Identification Number: https://doi.org/10.3390/jimaging5010007
SWORD Depositor: Symplectic Elements
Depositing User: Symplectic Elements
Date Deposited: 09 Apr 2019 14:10
Last Modified: 09 Apr 2019 14:10
URI: http://shura.shu.ac.uk/id/eprint/24382

Actions (login required)

View Item View Item

Downloads

Downloads per month over past year

View more statistics