A Seven-Valued Full Adder/Subtractor Architecture

MOKHTARI, Ali and KABIRI, Peyman (2018). A Seven-Valued Full Adder/Subtractor Architecture. In: 3rd International Conference on Electrical Engineering. Tehran-Iran, Civilica, 1-12.

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Abstract

Current generation of computers is based on binary logic. There are two types or operations executed in this generation i.e., mathematical and logical operations. Logical instructions use binary logic operations while the mathematical operations yet again use the mathematical operations based on binary logic. This article introduces a new idea based on Multi-Valued Logic (MVL) to build a full adder. Here mathematical and logical operations are considered separately. The reported work only considers mathematical operation and more specifically the full adder. The proposed full-adder circuit is based on Operational Amplifier (Op-Amp) and uses MVL with seven electrical levels for its design. This work is implemented in voltage mode and it is a step towards a new generation of computers. Schematic, layout, design and test results for the proposed full-adder are reported in the article.

Item Type: Book Section
Uncontrolled Keywords: Multi-valued logic, Multi-valued full adder, Op-Amp based full adder
SWORD Depositor: Symplectic Elements
Depositing User: Symplectic Elements
Date Deposited: 11 Mar 2019 09:30
Last Modified: 11 Mar 2019 09:45
URI: http://shura.shu.ac.uk/id/eprint/24215

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