FPGA implementation of a MIMO DFE in 40 GB/S DQPSK optical links

EMERETLIS, Andreas, KELEFOURAS, Vasileios, THEODORIDIS, George, NANOU, Maki, GEORGOULAKIS, Kwnstantinos and GLENTIS, Othon (2015). FPGA implementation of a MIMO DFE in 40 GB/S DQPSK optical links. In: 2015 23rd European Signal Processing Conference (EUSIPCO). IEEE, 1581-1585.

EUSIPCO15_Emeretlis_Andreas_2.pdf - Accepted Version
All rights reserved.

Download (2MB) | Preview
Official URL: https://ieeexplore.ieee.org/document/7362650/
Link to published version:: https://doi.org/10.1109/EUSIPCO.2015.7362650


In this paper, an FPGA implementation of a Multi Input Multi Output (MIMO) Decision Feedback equalizer (DFE) is proposed, for the electronic compensation of the impairments in 40Gb/s Intensity Modulated Direct Detection (IM/DD) optical communication links employing NRZ DQPSK signaling. The proposed equalizer is used for the electronic compensation the residual Chromatic Dispersion (CD) along the installed optically compensated optical paths. The required processing rate is achieved by applying intensive pipelining and parallelism in the original architecture of the equalizer. At the given processing rate, a 8-input 2-output DFE involving three taps feedforward filtering and two taps backward filtering is implemented on a single, cutting edge technology, Xilinx FPGA device.

Item Type: Book Section
Additional Information: Paper presented at EUSIPCO 15,31 Aug.-4 Sept. 2015, Nic, France. Electronic ISSN: 2076-1465 INSPEC Accession Number: 15671836
Identification Number: https://doi.org/10.1109/EUSIPCO.2015.7362650
Page Range: 1581-1585
Depositing User: Vasileios Kelefouras
Date Deposited: 09 May 2018 12:58
Last Modified: 18 Mar 2021 14:47
URI: https://shura.shu.ac.uk/id/eprint/18372

Actions (login required)

View Item View Item


Downloads per month over past year

View more statistics