Near-Optimal Microprocessor and Accelerators Codesign with Latency and Throughput Constraints

KRITIKAKOU, Angeliki, CATTHOOR, Francky, ATHANASIOU, George S., KELEFOURAS, Vasileios and GOUTIS, Costas (2013). Near-Optimal Microprocessor and Accelerators Codesign with Latency and Throughput Constraints. ACM Transactions on Architecture and Code Optimization, 10 (2), 6:1-6:25.

Full text not available from this repository.

Abstract

A systematic methodology for near-optimal software/hardware codesign mapping onto an FPGA platform with microprocessor and HW accelerators is proposed. The mapping steps deal with the inter-organization, the foreground memory management, and the datapath mapping. A step is described by parameters and equations combined in a scalable template. Mapping decisions are propagated as design constraints to prune suboptimal options in next steps. Several performance-area Pareto points are produced by instantiating the parameters. To evaluate our methodology we map a real-time bio-imaging application and loop-dominated benchmarks.

Item Type:	Article
Uncontrolled Keywords:	FPGA, area reduction, near optimal, real-time behavior
Departments - Does NOT include content added after October 2018:	Faculty of Science, Technology and Arts > Department of Computing
Identification Number:	https://doi.org/10.1145/2459316.2459317
Page Range:	6:1-6:25
Depositing User:	Vasileios Kelefouras
Date Deposited:	05 Apr 2018 13:35
Last Modified:	18 Mar 2021 15:19
URI:	https://shura.shu.ac.uk/id/eprint/18365

Actions (login required)

View Item

Downloads

Publication Metrics