Near-Optimal Microprocessor and Accelerators Codesign with Latency and Throughput Constraints

KRITIKAKOU, Angeliki, CATTHOOR, Francky, ATHANASIOU, George S., KELEFOURAS, Vasileios and GOUTIS, Costas (2013). Near-Optimal Microprocessor and Accelerators Codesign with Latency and Throughput Constraints. ACM Transactions on Architecture and Code Optimization, 10 (2), 6:1-6:25.

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Link to published version:: 10.1145/2459316.2459317


A systematic methodology for near-optimal software/hardware codesign mapping onto an FPGA platform with microprocessor and HW accelerators is proposed. The mapping steps deal with the inter-organization, the foreground memory management, and the datapath mapping. A step is described by parameters and equations combined in a scalable template. Mapping decisions are propagated as design constraints to prune suboptimal options in next steps. Several performance-area Pareto points are produced by instantiating the parameters. To evaluate our methodology we map a real-time bio-imaging application and loop-dominated benchmarks.

Item Type: Article
Uncontrolled Keywords: FPGA, area reduction, near optimal, real-time behavior
Departments: Arts, Computing, Engineering and Sciences > Computing
Identification Number: 10.1145/2459316.2459317
Depositing User: Vasileios Kelefouras
Date Deposited: 05 Apr 2018 13:35
Last Modified: 05 Apr 2018 13:35

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