A template-based methodology for efficient microprocessor and FPGA accelerator co-design

KRITIKAKOU, Angeliki, CATTHOOR, Francky, ATHANASIOU, George, KELEFOURAS, Vasileios and GOUTIS, Costas E. (2013). A template-based methodology for efficient microprocessor and FPGA accelerator co-design. In: 2012 International Conference on Embedded Computer Systems (SAMOS). IEEE, 15-22.

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Official URL: https://ieeexplore.ieee.org/document/6404153/
Link to published version:: 10.1109/SAMOS.2012.6404153

Abstract

Embedded applications usually require Software/Hardware (SW/HW) designs to meet the hard timing constraints and the required design flexibility. Exhaustive exploration for SW/HW designs is a very time consuming task, while the adhoc approaches and the use of partially automatic tools usually lead to less efficient designs. To support a more efficient codesign process for FPGA platforms we propose a systematic methodology to map an application to SW/HW platform with a custom HW accelerator and a microprocessor core. The methodology mapping steps are expressed through parametric templates for the SW/HW Communication Organization, the Foreground (FG) Memory Management and the Data Path (DP) Mapping. Several performance-area tradeoff design Pareto points are produced by instantiating the templates. A real-time bioimaging application is mapped on a FPGA to evaluate the gains of our approach, i.e. 44,8% on performance compared with pure SW designs and 58% on area compared with pure HW designs.

Item Type: Book Section
Departments: Arts, Computing, Engineering and Sciences > Computing
Identification Number: 10.1109/SAMOS.2012.6404153
Depositing User: Vasileios Kelefouras
Date Deposited: 17 May 2018 13:47
Last Modified: 17 May 2018 14:08
URI: http://shura.shu.ac.uk/id/eprint/18350

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