A methodology for speeding up fast fourier transform focusing on memory architecture utilization

KELEFOURAS, Vasileios, ATHANASIOU, George, ALACHIOTIS, Nikolaos, MICHAIL, Harris E., KRITIKAKOU, Angeliki and GOUTIS, Costas E. (2011). A methodology for speeding up fast fourier transform focusing on memory architecture utilization. IEEE Transactions on Signal Processing, 59 (12), 6217-6226.

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Official URL: http://ieeexplore.ieee.org/document/6021384/
Link to published version:: https://doi.org/10.1109/TSP.2011.2168525
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    Abstract

    Several SOA (state of the art) self-tuning software libraries exist, such as the Fastest Fourier Transform in the West (FFTW) for fast Fourier transform (FFT). FFT is a highly important kernel and the performance of its software implementations depends on the memory hierarchy's utilization. FFTW minimizes register spills and data cache accesses by finding a schedule that is independent of the number of the registers and of the number of levels and size of the cache, which is a serious drawback. In this paper, a new methodology is presented, achieving improved performance by focusing on memory hierarchy utilization. The proposed methodology has three major advantages. First, the combination of production and consumption of butterflies' results, data reuse, FFT parallelism, symmetries of twiddle factors and also additions by zeros and multiplications by zeros and ones when twiddle factors are zero or one, are fully and simultaneously exploited. Second, the optimal solution is found according to the number of the registers, the data cache sizes, the number of the levels of data cache hierarchy, the main memory page size, the associativity of the data caches and the data cache line sizes, which are also considered simultaneously and not separate. Third, compilation time and source code size are very small compared with FFTW. The proposed methodology achieves performance gain about 40% (speed-up of 1.7) for architectures with small data cache sizes where memory management has a larger effect on performance and 20% (speed-up of 1.25) on average for architectures with large data cache sizes (Pentium) in comparison with FFTW.

    Item Type: Article
    Additional Information: INSPEC Accession Number: 12358056
    Departments - Does NOT include content added after October 2018: Faculty of Science, Technology and Arts > Department of Computing
    Identification Number: https://doi.org/10.1109/TSP.2011.2168525
    Page Range: 6217-6226
    Depositing User: Vasileios Kelefouras
    Date Deposited: 04 Jun 2018 15:04
    Last Modified: 04 Jun 2018 15:04
    URI: http://shura.shu.ac.uk/id/eprint/18334

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