Power Efficient Dataflow Design for a Heterogeneous Smart Camera Architecture

BHOWMIK, Deepayan, GARCIA, Paulo, WALLACE, Andrew, STEWART, Robert and MICHAELSON, Greg (2017). Power Efficient Dataflow Design for a Heterogeneous Smart Camera Architecture. In: Conference on Design and Architectures for Signal and Image Processing (DASIP 2017), Dresden, Germany, 27-29 September 2017. (In Press)

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Abstract

Visual attention modelling characterises the scene to segment regions of visual interest and is increasingly being used as a pre-processing step in many computer vision applications including surveillance and security. Smart camera architectures are an emerging technology and a foundation of security and safety frameworks in modern vision systems. In this paper, we present a dataflow design of a visual saliency based camera architecture targeting a heterogeneous CPU+FPGA platform to propose a smart camera network infrastructure. The proposed design flow encompasses image processing algorithm implementation, hardware & software integration and network connectivity through a unified model. By leveraging the properties of the dataflow paradigm, we iteratively refine the algorithm specification into a deployable solution, addressing distinct requirements at each design stage: from algorithm accuracy to hardware-software interactions, real-time execution and power consumption. Our design achieved real-time run time performance and the power consumption of the optimised asynchronous design is reported at only 0.25 Watt. The resource usages on a Xilinx Zynq platform remains significantly low.

Item Type: Conference or Workshop Item (Paper)
Research Institute, Centre or Group: Cultural Communication and Computing Research Institute > Communication and Computing Research Centre
Depositing User: Deepayan Bhowmik
Date Deposited: 31 Jul 2017 13:41
Last Modified: 31 Jul 2017 13:49
URI: http://shura.shu.ac.uk/id/eprint/16301

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