A dataflow IR for memory efficient RIPL compilation to FPGAs

STEWART, Robert, MICHAELSON, Greg, BHOWMIK, Deepayan, GARCIA, Paulo and WALLACE, Andy (2016). A dataflow IR for memory efficient RIPL compilation to FPGAs. In: CARRETERO, Jesus, GARCIA-BLAS, Javier, GERGEL, Victor, VOEVODIN, Vladimir, MEYEROV, Iosif, RICO-GALLEGO, Juan A., DIAZ-MARTIN, Juan C., ALONSO, Pedro, DURILLO, Juan, GARCIA SANCHEZ, Jose Daniel, LASTOVETSKY, Alexey L., MAROZZO, Fabrizio, LIU, Qin, BHUIYAN, Zakirul Alam, FURLINGER, Karl, WEIDENDORFER, Josef and GARCIA, Jose, (eds.) Algorithms and architectures for parallel processing : ICA3PP 2016 Collocated Workshops: SCDT, TAPEMS, BigTrust, UCER, DLMCS, Granada, Spain, December 14-16, 2016, Proceedings. Lecture Notes in Computer Science (10049). Springer, 174-188.

Bhowmik - Dataflow IR for memory efficient RIPL (AM).pdf - Accepted Version
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Official URL: http://link.springer.com/chapter/10.1007%2F978-3-3...
Link to published version:: https://doi.org/10.1007/978-3-319-49956-7_14
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    Field programmable gate arrays (FPGAs) are fundamentally different to fixed processors architectures because their memory hierarchies can be tailored to the needs of an algorithm. FPGA compilers for high level languages are not hindered by fixed memory hierarchies. The constraint when compiling to FPGAs is the availability of resources. In this paper we describe how the dataflow intermediary of our declarative FPGA image processing DSL called RIPL (Rathlin Image Processing Language) enables us to constrain memory. We use five benchmarks to demonstrate that memory use with RIPL is comparable to the Vivado HLS OpenCV library without the need for language pragmas to guide hardware synthesis. The benchmarks also show that RIPL is more expressive than the Darkroom FPGA image processing language.

    Item Type: Book Section
    Additional Information: Series ISSN - 0302-9743 Paper original presented at the International Workshop on Data Locality in Modern Computing Systems (DLMCS 2016)
    Uncontrolled Keywords: Domain specific languages – FPGAs – Data locality
    Departments - Does NOT include content added after October 2018: Faculty of Science, Technology and Arts > Department of Computing
    Identification Number: https://doi.org/10.1007/978-3-319-49956-7_14
    Page Range: 174-188
    Depositing User: Deepayan Bhowmik
    Date Deposited: 18 Jan 2017 12:08
    Last Modified: 02 Jul 2020 10:36
    URI: http://shura.shu.ac.uk/id/eprint/14205

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