Profile Guided Dataflow Transformation for FPGAs and CPUs

STEWART, Robert, BHOWMIK, Deepayan, WALLACE, Andrew and MICHAELSON, Greg (2015). Profile Guided Dataflow Transformation for FPGAs and CPUs. Journal of Signal Processing Systems, 87 (1), 3-20.

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Official URL: http://link.springer.com/article/10.1007/s11265-01...
Link to published version:: https://doi.org/10.1007/s11265-015-1044-y
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    Abstract

    This paper proposes a new high-level approach for optimising field programmable gate array (FPGA) designs. FPGA designs are commonly implemented in low-level hardware description languages (HDLs), which lack the abstractions necessary for identifying opportunities for significant performance improvements. Using a computer vision case study, we show that modelling computation with dataflow abstractions enables substantial restructuring of FPGA designs before lowering to the HDL level, and also improve CPU performance. Using the CPU transformations, runtime is reduced by 43 %. Using the FPGA transformations, clock frequency is increased from 67MHz to 110MHz. Our results outperform commercial low-level HDL optimisations, showcasing dataflow program abstraction as an amenable computation model for highly effective FPGA optimisation.

    Item Type: Article
    Departments - Does NOT include content added after October 2018: Faculty of Science, Technology and Arts > Department of Computing
    Identification Number: https://doi.org/10.1007/s11265-015-1044-y
    Page Range: 3-20
    Depositing User: Deepayan Bhowmik
    Date Deposited: 07 Nov 2016 14:24
    Last Modified: 23 Jun 2020 14:00
    URI: http://shura.shu.ac.uk/id/eprint/13807

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