Digital tanlock loop architecture with no delay

AL-ALI, Omar Al-Kharji, ANANI, Nader, AL-ARAJI, Saleh, AL-QUTAYRI, Mahmoud and PONNAPALLI, Prasad (2012). Digital tanlock loop architecture with no delay. International Journal of Electronics, 99 (2), 179-195.

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Official URL: http://dx.doi.org/10.1080/00207217.2011.623271
Link to published version:: 10.1080/00207217.2011.623271

Abstract

This article proposes a new architecture for a digital tanlock loop which eliminates the time-delay block. The �=2 (rad) phase shift relationship between the two channels, which is generated by the delay block in the conventional timedelay digital tanlock loop (TDTL), is preserved using two quadrature sampling signals for the loop channels. The proposed system outperformed the original TDTL architecture, when both systems were tested with frequency shift keying input signal. The new system demonstrated better linearity and acquisition speed as well as improved noise performance compared with the original TDTL architecture. Furthermore, the removal of the time-delay block enables all processing to be digitally performed, which reduces the implementation complexity. Both the original TDTL and the new architecture without the delay block were modelled and simulated using ATLAB/Simulink. Implementation issues, including complexity and relation to simulation of both architectures, are also addressed.

Item Type: Article
Research Institute, Centre or Group: Materials and Engineering Research Institute > Thin Films Research Centre > Electronic Materials and Sensors Research Group
Identification Number: 10.1080/00207217.2011.623271
Depositing User: Nader Anani
Date Deposited: 03 Jul 2015 09:48
Last Modified: 19 Oct 2016 21:17
URI: http://shura.shu.ac.uk/id/eprint/10150

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