Performance evaluation of the time delay digital tanlock loop architectures

AL-KHARJI AL-ALI, Omar, ANANI, Nader, AL-ARAJI, Saleh, AL-QUTAYRI, Mahmoud and PONNAPALLI, Prasad (2015). Performance evaluation of the time delay digital tanlock loop architectures. International Journal of Electronics, 103 (1), 88-112.

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Link to published version:: 10.1080/00207217.2015.1036310

Abstract

This article presents the architectures, theoretical analyses and testing results of modified time delay digital tanlock loop (TDTLs) system. The modifications to the original TDTL architecture were introduced to overcome some of the limitations of the original TDTL and to enhance the overall performance of the particular systems. The limitations addressed in this article include the non-linearity of the phase detector, the restricted width of the locking range and the overall system acquisition speed. Each of the modified architectures was tested by subjecting the system to sudden positive and negative frequency steps and comparing its response with that of the original TDTL. In addition, the performance of all the architectures was evaluated under noise-free as well as noisy environments. The extensive simulation results using MATLAB/SIMULINK demonstrate that the new architectures overcome the limitations they addressed and the overall results confirmed significant improvements in performance compared to the conventional TDTL system.

Item Type: Article
Research Institute, Centre or Group: Materials and Engineering Research Institute > Thin Films Research Centre > Electronic Materials and Sensors Research Group
Identification Number: 10.1080/00207217.2015.1036310
Related URLs:
Depositing User: Nader Anani
Date Deposited: 09 Jun 2015 10:15
Last Modified: 20 Oct 2016 00:22
URI: http://shura.shu.ac.uk/id/eprint/10148

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